CYW4343X
10.1.6.3 Long Frame Sync, Master Mode
Figure 35. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
PCM_OUT
8
High Impedance
7
Bit 0
Bit 0
Bit 1
Bit 1
5
6
PCM_IN
Table 11. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Ref No.
Characteristics
Minimum
Typical
Maximum
12
Unit
1
2
3
4
5
6
7
8
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
–
–
–
–
–
–
–
–
–
MHz
ns
41
41
0
–
–
ns
25
25
–
ns
0
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
0
25
ns
Document No. 002-14797 Rev. *H
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