CYW4343X
Table 13. Example of Common Baud Rates
Actual Rate
Desired Rate
Error (%)
4000000
3692000
3000000
2000000
1500000
1444444
921600
460800
230400
115200
57600
4000000
3692308
3000000
2000000
1500000
1454544
923077
461538
230796
115385
57692
0.00
0.01
0.00
0.00
0.00
0.70
0.16
0.16
0.17
0.16
0.16
0.00
0.16
0.00
0.16
0.00
38400
38400
28800
28846
19200
19200
14400
14423
9600
9600
UART timing is defined in Figure 37 and Table 14.
Figure 37. UART Timing
UART_CTS_N
1
2
UART_TXD
Midpoint of STOP bit
Midpoint of STOP bit
UART_RXD
3
UART_RTS_N
Table 14. UART Timing Specifications
Characteristics Minimum
Ref No.
Typical
Maximum
Unit
1
2
Delay time, UART_CTS_N low to UART_TXD valid
–
–
–
–
1.5
Bit periods
Bit periods
Setup time, UART_CTS_N high before midpoint
of stop bit
0.5
3
Delay time, midpoint of stop bit to UART_RTS_N high
–
–
0.5
Bit periods
Document No. 002-14797 Rev. *H
Page 53 of 128
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