CYW4343X
9. Microprocessor and Memory Unit for Bluetooth
The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and
JTAG interface units. It runs software from the link control (LC) layer up to the host controller interface (HCI).
The ARM core is paired with a memory unit that contains 576 KB of ROM for program storage and boot ROM, and 160 KB of RAM
for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset (POR) to enable the same
device to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches
may be downloaded from the host to the CYW4343X through the UART transports.
9.1 RAM, ROM, and Patch Memory
The CYW4343X Bluetooth core has 160 KB of internal RAM which is mapped between general purpose scratch-pad memory and
patch memory, and 576 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory
is used for bug fixes and feature additions to ROM memory code.
9.2 Reset
The CYW4343X has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT POR circuit is out
of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.
10. Bluetooth Peripheral Transport Unit
10.1 PCM Interface
The CYW4343X supports two independent PCM interfaces that share pins with the I2S interfaces. The PCM interface on the
CYW4343X can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW4343X generates the
PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are
inputs to the CYW4343X. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific
HCI commands.
10.1.1 Slot Mapping
The CYW4343X supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sam-
ple interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz,
or 1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive
PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots
to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the
PCM clock during the last bit of the slot.
10.1.2 Frame Synchronization
The CYW4343X supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchroniza-
tion mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization sig-
nal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident
with the first bit of the first slot.
10.1.3 Data Formatting
The CYW4343X may be configured to generate and accept several different data formats. For conventional narrowband speech
mode, the CYW4343X uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to sup-
port various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0’s, 1’s, a
sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
Document No. 002-14797 Rev. *H
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