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BCM4343SKUBG 参数 Datasheet PDF下载

BCM4343SKUBG图片预览
型号: BCM4343SKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip IEEE 802.11 b/g/n MAC/ Baseband/Radio with Bluetooth 4.1,an FM Receiver, and Wireless Charging]
分类和应用: 无线
文件页数/大小: 127 页 / 10739 K
品牌: CYPRESS [ CYPRESS ]
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CYW4343X  
2
10.3 I S Interface  
The CYW4343X supports an independent I2S digital audio port for high-fidelity FM audio or Bluetooth audio. The I2S interface sup-  
ports both master and slave modes. The I2S signals are:  
I2S Clock: I2S SCK  
I2S Word Select: I2S WS  
I2S Data Out: I2S SDO  
I2S Data In: I2S SDI  
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO is always an output. The channel  
word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the  
I2S specification. The MSB of each data word is transmitted one bit-clock cycle after the I2S WS transition, synchronous with the fall-  
ing edge of the bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is  
high. Data bits sent by the CYW4343X are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on  
the rising edge of I2S_SSCK.  
The clock rate in master mode is either of the following:  
48 kHz x 32 bits per frame = 1.536 MHz  
48 kHz x 50 bits per frame = 2.400 MHz  
The master clock is generated from the input reference clock using an N/M clock divider.  
In slave mode, clock rates up to 3.072 MHz are supported.  
10.3.1 I2S Timing  
Note: Timing values specified in Table 15 are relative to high and low threshold levels  
Table 15. Timing for I2S Transmitters and Receivers  
Transmitter  
Lower LImit Upper Limit  
Receiver  
Lower Limit Upper Limit  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Notes  
Clock period T  
T
T
1
tr  
r
Master mode: Clock generated by transmitter or receiver.  
High tHC  
Low tLC  
0.35T  
0.35T  
0.35T  
0.35T  
2
2
tr  
tr  
tr  
tr  
Slave mode: Clock accepted by transmitter or receiver.  
High tHC  
0.35T  
0.35T  
0.35T  
0.35T  
3
3
4
tr  
tr  
tr  
tr  
Low tLC  
Rise time tRC  
0.15T  
tr  
Transmitter  
Delay tdtr  
0
0.8T  
5
4
Hold time thtr  
Receiver  
Setup time tsr  
Hold time thr  
0.2T  
0
6
6
r
Document No. 002-14797 Rev. *H  
Page 54 of 128  
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