CYW4343X
10.1.6.2 Short Frame Sync, Slave Mode
Figure 34. PCM Timing Diagram (Short Frame Sync, Slave Mode)
1
2
3
PCM_BCLK
4
5
PCM_SYNC
PCM_OUT
9
High Impedance
8
6
7
PCM_IN
Table 10. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)
Characteristics Minimum Typical Maximum
Ref No.
Unit
1
2
3
4
5
6
7
8
9
PCM bit clock frequency
–
–
–
–
–
–
–
–
–
–
12
–
MHz
ns
PCM bit clock low
PCM bit clock high
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
41
41
8
–
ns
–
ns
8
–
ns
0
25
–
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
0
25
ns
Document No. 002-14797 Rev. *H
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