CYW4343X
Note:
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The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to
handle the data transfer rate.
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At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this
reason, tHC and tLC are specified with respect to T.
In slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect
the signal. As long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.
Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow
clock edge can result in tdtr not exceeding tRC, which means thtr becomes zero or negative. Therefore, the transmitter has
to guarantee that thtr is greater than or equal to zero, as long as the clock rise-time, tRC, does not exceed tRCmax, where
tRCmax is not less than 0.15Ttr.
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To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal
and T, always giving the receiver sufficient setup time.
The data setup and hold time must not be less than the specified receiver setup and hold time.
Note: The time periods specified in Figure 38 and Figure 39 are defined by the transmitter speed. The receiver specifications must
match transmitter performance.
Figure 38. I2S Transmitter Timing
T
tRC*
tLC > 0.35T
tHC > 0.35T
VH = 2.0V
VL = 0.8V
SCK
thtr > 0
tdtr < 0.8T
SD and WS
T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr
* tRC is only relevant for transmitters in slave mode.
Document No. 002-14797 Rev. *H
Page 55 of 128
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