CYW43362
14. Interface Timing and AC Characteristics
Note: Values in this document are design goals and are subject to change based on the results of device characterization.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in
Table 13 on page 41 and Table 15 on page 42. Functional operation outside of these limits is not guaranteed.
14.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 25 and Table 25 on page 53.
Figure 25. SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(min)
Table 25. SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency—Data Transfer mode
Frequency—Identification mode
Clock low time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
0
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock fall time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time—Data Transfer mode
Document No. 002-14779 Rev. *G
tODLY
0
–
14
ns
Page 53 of 60
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