CYW43362
Table 25. SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Output delay time—Identification mode
tODLY
0
–
50
ns
a. Timing is based on CL 40 pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
14.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 26 and Table 26.
Figure 26. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 26. SDIO Bus Timing a Parameters (High-Speed Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
Clock high time
–
ns
Clock rise time
3
ns
Clock fall time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup Time
Input hold Time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total system capacitance (each line)
CL
40
a. Timing is based on CL 40pF load on CMD and Data.
b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
Document No. 002-14779 Rev. *G
Page 54 of 60
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