CYW43362
13. System Power Consumption
Note: Table 24 shows typical values.
Power consumption referenced to VBAT @ 3.6V, 20°C, VDDIO = 1.8V, CBUCK out = 1.5V.
Table 24. System Power Consumption
WLAN Operational Modes
Total (Ivbat)
OFF1
11 µA
40 µA
OFF2
IDLE
185 µA
200 µA
SLEEP5
Rx (Listen)3
Rx (Active)4
Power Save6, 9
52 mA
59 mA
1.9 mA
320 mA
270 mA
260 mA
Tx CCK (11 Mbps at 18.5 dBm)7, 11
Tx OFDM (54 Mbps at 15.5 dBm)8, 11
Tx OFDM (65 Mbps at 14.5 dBm)10, 11
Note 1: WL_RST_N = Low, VDDIO is not present
Note 2: WL_RST_N = Low, VDDIO is present
Note 3: Carrier Sense (CCA) when no carrier present
Note 4: Carrier Sense (CS) detect/Packet Rx
Note 5: Intra-beacon Sleep
Note 6: Beacon Interval = 102.4 ms, DTIM = 1, Beacon duration = 1 ms @1 Mbps.
Integrated Sleep + wakeup + Beacon Rx current over 1 DTIM interval.
Note 7: CCK power at chip port. Duty cycle is 100%. Includes PA contribution at 3.6V.
Note 8: OFDM power at chip port. Duty cycle is 100%. Includes PA contribution at 3.6V.
Note 9: In WLAN power-saving mode, the following blocks are powered down: Crystal oscillator, Baseband PLL, AFE, RF PLL, Radio
Note 10: OFDM power at chip port is 16 dBm, duty cycle is 100%, includes PA contribution at 3.6V.
The above blocks are turned ON in the required order with sufficient time for them to settle. This sequencing is done by the PMU controller
that controls the settling time for each of the blocks. It also has information to determine the order in which the blocks should be turned
ON. The settling times and the dependency order are programmable in the PMU controller. The default CLK settling time is set to 8 ms
at power-up. It can be reduced after power-up.
Note 11: Absolute junction temperature limits maintained through active thermal monitoring and dynamic Tx duty cycle limiting.
Document No. 002-14779 Rev. *G
Page 52 of 60
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