CYW43362
Table 20. Core Buck Regulator (Cont.)
Specification
Notes
Minimum Typical Maximum Units
Start-up time from
power down
–
–
–
1350
1500
µs
Burst to PWM mode
transient voltage error
Ensure load current < 200 mA during
a mode change
–
160
mV
External inductor
See preferred inductor list
–
–
1.5
4.7
–
–
µH
µF
External output capacitor
Ceramic, X5R, 0402, Cap-ESR < 4 mΩ
ESL < 700 pH at 3.2 MHz, ±20%, 6.3V
External input
capacitor
For SR_VDDBAT1 pins,
–
4.7
–
–
–
µF
µs
ceramic, X5R, 0603, Cap-ESR < 4 mΩ
at 3.2 MHz, ±10%, 6.3V
Input supply voltage
ramp-up time
0 to 4.3V
40
a. The maximum continuous supply voltage is 4.8V. Brief spikes above this 4.8V can be tolerated. Specifically, voltages as high as 5.5V for up to
10 seconds cumulative duration over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds cumulative duration
over the lifetime of the device are allowed.
b. These are not load or line step transient tests.
c. More capacitance can be used to reduce the transient error at the output.
d. VBAT < 4.3V. Inductor DCR < 137.5 mΩ, ACR < 1Ω.
An efficiency plot for the CBUCK regulator is shown in Figure 24. The plot shows typical performance for nominal process silicon,
Vout = 1.8V, VBAT = 3.6V, and temperature = 25°C.
Figure 24. CBUCK Efficiency
100
90
80
70
60
50
40
PWM mode
Burst mode
30
20
10
0
0.1
1
10
100
1000
Load in mA
Document No. 002-14779 Rev. *G
Page 49 of 60
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