PRELIMINARY
CYW43340
16.6 LNLDO
Table 40. LNLDO Specifications
Specification
Notes
Min
1.3
Typ
1.35
Max
1.5
Units
Input supply voltage, Vin
Min = 1.2Vo + 0.1V = 1.3V.
V
Dropout voltage requirement must be met under
maximum load.
Output current
–
0.1
1.1
–
104
mA
V
Output voltage, Vo
Programmable in 25 mV steps.
Default = 1.2V
1.2
1.275
Dropout voltage
At maximum load
–
–
–
100
+4
mV
%
Output voltage DC
accuracya
includes line/load regulation, load from 0.1 to
150 mA
–4
Quiescent current
Line regulation
Load regulation
Leakage current
Output noise
No load
–
–
–
–
–
44
–
–
µA
V
in from (Vo + 0.1V) to 1.5V, max load
7
mV/V
µV/mA
µA
Load from 1 mA to 104 mA
Power-down
15
–
25
10
@30 kHz, 60 mA load, Co = 1 µF
@100 kHz, 60 mA load, Co = 1 µF
–
60
35
nV/root-Hz
nV/root-Hz
PSRR
@ 1kHz, input > 1.3V, Co= 1 µF,
Vo = 1.2V
20
–
–
–
dB
Start-up time of PMU
VIO up and steady. Time from the REG_ON rising –
edge to the LNLDO reaching 1.2V. Includes 256
µs vddc_ok_o delay.
1106
µs
LDO turn-on time
Chip already powered up.
–
–
–
–
180
150
µs
In-rush current during turn-on
From its output capacitor in a fully-discharged
state
mA
External output capacitor,
Co
Total ESR (trace/capacitor): 30–200 mΩ
0.67c
–
1
1
–
–
µF
µF
b
External input capacitor
Only use an external input capacitor at the
VDD_LDO pin if it is not supplied from the CBUCK
output.
Total ESR (trace/capacitor): 30–200 mΩ
a.Load from 0.1 to 104 mA.
b.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.
c.The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-14943 Rev. *L
Page 81 of 96
CYPRESS [ CYPRESS ]
