PRELIMINARY
CYW43340
18. Interface Timing and AC Characteristics
18.1 SDIO Timing
18.1.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 31 and Table 43.
Figure 31. SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(min)
Table 43. SDIO Bus Timinga Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
fOD
tWL
tWH
tTLH
tTHL
0
kHz
ns
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock low time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
a.Timing is based on CL 40pF load on CMD and Data.
b.min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
tODLY
tODLY
0
0
–
–
14
50
ns
ns
Document Number: 002-14943 Rev. *L
Page 84 of 96
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