PRELIMINARY
CYW43340
16. Internal Regulator Electrical Specifications
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
Functional operation is not guaranteed outside of the specification limits provided in this section.
16.1 Core Buck Switching Regulator
Table 35. Core Buck Switching Regulator (CBUCK) Specifications
Specification
Notes
Min
2.9
Typ
3.6
Max
4.8a
Units
Input supply voltage (DC),
VBAT
DC voltage range inclusive of disturbances.
V
PWM mode switching
frequency, Fsw
Forced PWM without FLL enabled.
2.8
3.6
–
4
5.2
4.4
372b
–
MHz
MHz
mA
Forced PWM with FLL enabled.
4
PWM output current
Output current limit
Output voltage range
–
–
–
–
1390
1.35
mA
Programmable, 30 mV steps.
Default = 1.35V (bits = 0000).
1.2
1.5
Volts
PWM output voltage DC accuracy
Includes load and line regulation.
Forced PWM mode.
–4
–
4
%
Total DC accuracy after trim.
–2
–
–
7
2
%
PWM ripple voltage, static
Measure with 20 MHz BW limit.
Static Load. Max ripple based on:
VBAT < 4.8V, Vout = 1.35V, Fsw = 4 MHz, 2.2 µH
inductor, L > 1.05 µH,
20
mVpp
capacitor + Board total-ESR < 20 mΩ, Cout >
1.9 µF, ESL < 200 pH.
PWM mode peak efficiency
2.5 x 2 mm LQM2HPN2R2NG0,
L = 2 µH, DCR = 80 mΩ ±25%,
79
78
74
67
85
84
81
77
–
–
–
–
%
%
%
%
(Peak efficiency is at 200 mAload. The ACR < 1Ω.
following conditions apply to all
inductor types: Forced PWM, 200 mA,
Vout = 1.35V, VBAT = 3.6V, Fsw = 4
MHz, at 25°C.)
0805-size LQM21PN2R2NGC,
L = 2.1 µH, DCR=230 mΩ ±25%,
ACR < 2Ω.
0603-size MIPSTZ1608D2R2B,
L = 1 µH, DCR = 240 mΩ ±25%,
ACR < 2Ω.
PFM mode efficiency
LPOM efficiency
10 mA load current, Vout = 1.35V,
VBAT = 3.6V,
20C Cap + Board total-ESR < 20 mΩ, Cout =
4.7 µF, ESL < 200 pH, FLL= OFF
0603-size MIPSTZ1608D2R2B,
L = 2.2 µH, DCR = 240 mΩ ±25%,
ACR < 2Ω.
1 mA load current, Vout = 1.35V,
VBAT = 3.6V,
55
65
–
%
20C Cap + board total-ESR < 20 mΩ, Cout =
4.7 µF, ESL < 200 pH, FLL = OFF
0603-size MIPSTZ1608D2R2B,
L = 2.2 µH, DCR = 240Ω ±25%,
ACR < 2Ω.
Start-up time from power down
VIO already on and steady.
Time from REG_ON rising edge to CLDO
reaching 1.2V.
–
903
1106
µs
Includes 256 µsec typical Vddc_ok_o delay.
Document Number: 002-14943 Rev. *L
Page 77 of 96
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