PRELIMINARY
CYW43340
Table 38. HISCDVDD LDO Specifications (Cont.)
Specification
PSRR at 10 kHz
Notes
Min
24
Typ
Max
Units
Input ≥ 1.35V, 50 to 300 pF, Vo = 1.2V
Load: 80 mA
–
–
–
–
–
dB
dB
Load: 40 mA
38
PSRR at 100 kHz
Input ≥ 1.35V, 50 to 300 pF, Vo = 1.2V
Load: 80 mA
15
27
dB
dB
Load: 40 mA
Output Capacitor, Co
Internal capacitor = Sum of supply decoupling –
caps and supply-to-ground routing parasitic
capacitance.
1000
pF
Output capacitor dependent on programming.
16.5 CLDO
Table 39. CLDO Specifications
Specification
Notes
Min
Typ
1.35
Max
1.5
Units
Input supply voltage, Vin
Min = 1.2 + 0.1V = 1.3V.
1.3
V
Dropout voltage requirement must be met under
maximum load.
Output current
–
0.1
1.1
–
150
mA
Output voltage, Vo
Programmable in 25 mV steps.
1.2
1.275
V
Default = 1.2V, load from 0.1–150 mA
Dropout voltage
Output voltage DC accuracya
At max load
–
–
–
–
100
+4
mV
%
Includes line/load regulation
–4
After trim, load from 0.1–150 mA, includes line/load –2
+2
%
regulation.
Vin > Vo + 0.1V.
Quiescent current
Line regulation
Load regulation
Leakage current
PSRR
No load
–
10
–
–
µA
Vin from (Vo + 0.1V) to 1.5V, maximum load
Load from 1 mA to 150 mA
Power-down
–
7
mV/V
µV/mA
µA
–
15
–
25
10
–
@1 kHz, Vin ≥ 1.5V, Co = 1 µF
20
–
–
dB
Start-up time of PMU
VIO up and steady. Time from the REG_ON rising
edge to the CLDO reaching 1.2V. Includes 256 µs
vddc_ok_o delay.
–
1106
µs
LDO turn-on time
Chip already powered up.
–
–
–
1
1
180
150
–
µs
In-rush current during turn-on
From its output capacitor in a fully-discharged state
Total ESR: 30 mΩ–200 mΩ
–
mA
µF
µF
b
External output capacitor, Co
0.67c
External input capacitor
Only use an external input capacitor at the VDD_LDO –
pin if it is not supplied from the CBUCK output. Total
ESR (trace/capacitor): 30 mΩ–200 mΩ
–
a.Load from 0.1 to 150 mA.
b.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.
c.The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-14943 Rev. *L
Page 80 of 96
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