PRELIMINARY
CYW43340
Table 35. Core Buck Switching Regulator (CBUCK) Specifications (Cont.)
Specification
External inductor, Lc
External output capacitor, Coutc
Notes
Min
Typ
2.2
Max
Units
µH
–
–
–
–
Ceramic, X5R, 0402, ESR < 30 mΩ at 4 MHz, 2d
±20%, 6.3V, 4.7 µF,
4.7
µF
Murata® GRM155R60J475M
External input capacitor, Cinc
For SR_VDDBATP5V pin.
Ceramic, X5R, 0603, ESR < 30 mΩ at 4 MHz,
0.67d
4.7
–
µF
±20%, 6.3V, 4.7 µF,
Murata GRM155R60J475M.
Input supply voltage ramp-up time
0 to 4.3V
40
–
100,000
µs
a.The maximum continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Volt-
ages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b.At junction temperature 125°C.
c.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.
d.The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.
16.2 3.3V LDO (LDO3P3)
Table 36. LDO3P3 Specifications
Parameters
Input supply voltage, Vin Minimum = Vo+0.2V = 3.5V (for Vo = 3.3V)
dropout voltage requirement must be met under max load for perfor-
Conditions
Min.
2.9
Typ.
3.6
Max.
4.8
Units
V
mance specs.
Nominal output voltage, Default = 3.3V
Vo
–
3.3
–
–
V
V
Output voltage program- Range
2.4
3.4
+5
mability
Accuracy at any step (including Line/Load regulation), load > 0.1 mA –5
%
Dropout voltage
Output current
Quiescent current
At maximum load
–
–
–
–
200
450
mV
mA
0.001
–
No load; Vin = Vo + 0.2V
Maximum load @ 450mA; Vin = Vo + 0.2V
66
4
85
4.5
µA
mA
Leakage current
Line regulation
Load regulation
Load step error
Powerdown mode (at 85°C junction temperature)
Vin from (Vo + 0.2V) to 4.8V, maximum load
load from 1–450 mA, Vin = 3.6V
–
–
–
–
1.5
5
µA
3.5
0.45
70
mV/V
mV/mA
mV
0.3
–
Load from 1mA-200mA-400mA in 1 q5s and
400mA-200mA-1mA in 1 µs; Vin ≥ (Vo + 0.2V);
Co = 4.7 µF
PSRR
VBAT ≥ 3.6V, Vo = 3.3V, Co = 4.7 µF,
maximum load, 100 Hz to 100 kHz
20
–
–
dB
LDO turn-on time
Output current limit
In-rush current
LDO turn-on time when rest of chip is up
–
160
800
250
µs
–
–
mA
mA
µF
Vin = Vo + 0.2V to 4.8V, Co = 4.7 µF, no load
–
280
External output
capacitor, Co
Ceramic, X5R, 0402,
(ESR: 5m-240mohm), ±10%, 10V
1.0
4.7
4.7
5.64
External input capacitor For SR_VDDBATA5V pin (shared with Bandgap) ceramic, X5R,
0402, ±10%, 10V.
–
–
µF
Not needed if sharing VBAT cap 4.7 µF with SR_VDDBATP5V.
Document Number: 002-14943 Rev. *L
Page 78 of 96
CYPRESS [ CYPRESS ]
