PRELIMINARY
CYW43340
18.1.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 32 and Table 44.
Figure 32. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 44. SDIO Bus Timinga Parameters (High-Speed Mode)
Parameter Symbol
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Minimum
Typical
Maximum
Unit
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
fOD
tWL
tWH
tTLH
tTHL
kHz
ns
Clock high time
–
ns
Clock rise time
3
ns
Clock low time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup Time
tISU
tIH
6
2
–
–
–
–
ns
ns
Input hold Time
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total system capacitance (each line)
a.Timing is based on CL 40pF load on CMD and Data.
b.min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
CL
40
Document Number: 002-14943 Rev. *L
Page 85 of 96
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