PRELIMINARY
CYW43340
8. WLAN Global Functions
8.1 WLAN CPU and Memory Subsystem
The CYW43340 includes an integrated ARM Cortex-M3™ processor with internal RAM and ROM. The ARM Cortex-M3 processor is
a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded
applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for
Thumb®-2 instruction set. ARM Cortex-M3 delivers 30% more performance gain over ARM7TDMI®.
At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It supports integrated sleep modes.
ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced
silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-
M3 supports extensive debug features including real time trace of program execution.
On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.
8.2 One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal 3072-bit One-Time Programmable (OTP) memory, which is
read by the system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the
MAC address can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test
tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state
can be altered during each programming cycle.
Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the
reference board design package.
8.3 GPIO Interface
On the WLBGA package, there are 8 GPIO pins available on the WLAN section of the CYW43340 that can be used to connect to
various external devices.
Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via
the GPIO control register.
8.4 External Coexistence Interface
An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such
as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance. The coexistence signals in Figure 19
and Table 15 can be enabled by software on the indicated GPIO pins.
Figure 19. LTE Coexistence Interface
GPIO5
WLAN_PRIORITY
GPIO3
WLAN
ERCX
LTE_TX
LTE_RX
GPIO2
BT
CYW4334X
LTE Chip
Document Number: 002-14943 Rev. *L
Page 34 of 96
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