PRELIMINARY
CYW43340
Table 15. External Coexistence Interface
Coexistence Signal
ERCX_TX_CONF/WLAN_PRIORITY
ERCX_FREQ/LTE_TX
GPIO Name
Type
Output
Comment
Notify LTE of request to sleep
GPIO_5
GPIO_3
GPIO_2
Input
Input
Notify WLAN RX of requirement to sleep
Notify WLAN TX to reduce TX power
ERCX_RF_ACTIVE/LTE_RX
8.5 UART Interface
One UART interface can be enabled by software as an alternate function on pins WL_GPIO4 and WL_GPIO_5. Provided primarily
for debugging during development, this UART enables the CYW43340 to operate as RS-232 data termination equipment (DTE) for
exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO
size of 64 × 8 in each direction.
8.6 JTAG Interface
The CYW43340 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character-
ization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
Document Number: 002-14943 Rev. *L
Page 35 of 96
CYPRESS [ CYPRESS ]
