欢迎访问ic37.com |
会员登录 免费注册
发布采购

BCM43340HKUBG 参数 Datasheet PDF下载

BCM43340HKUBG图片预览
型号: BCM43340HKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n MAC/Baseband/Radio with Integrated Bluetooth 4.0]
分类和应用:
文件页数/大小: 96 页 / 1349 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号BCM43340HKUBG的Datasheet PDF文件第28页浏览型号BCM43340HKUBG的Datasheet PDF文件第29页浏览型号BCM43340HKUBG的Datasheet PDF文件第30页浏览型号BCM43340HKUBG的Datasheet PDF文件第31页浏览型号BCM43340HKUBG的Datasheet PDF文件第33页浏览型号BCM43340HKUBG的Datasheet PDF文件第34页浏览型号BCM43340HKUBG的Datasheet PDF文件第35页浏览型号BCM43340HKUBG的Datasheet PDF文件第36页  
PRELIMINARY  
CYW43340  
Table 14. Timing for I2S Transmitters and Receivers  
Transmitter  
Lower LImit Upper Limit  
Receiver  
Lower Limit Upper Limit  
Min Max  
Notes  
Min  
Max  
Min  
Max  
Min  
Max  
Clock Period T  
T
T
1
tr  
r
Master Mode: Clock generated by transmitter or receiver  
High tHC  
Low tLC  
0.35T  
0.35T  
0.35T  
0.35T  
2
2
tr  
tr  
tr  
tr  
Slave Mode: Clock accepted by transmitter or receiver  
High tHC  
0.35T  
0.35T  
0.35T  
0.35T  
3
3
4
tr  
tr  
tr  
Low tLC  
tr  
Rise time tRC  
0.15T  
tr  
Transmitter  
Delay tdtr  
0
0.8T  
5
4
Hold time thtr  
Receiver  
Setup time tsr  
Hold time thr  
0.2T  
0
6
6
r
Note:  
The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the  
data transfer rate.  
At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason,  
tHC and tLC are specified with respect to T.  
In slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal.  
So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.  
Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock  
edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee  
that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.  
To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T,  
always giving the receiver sufficient setup time.  
The data setup and hold time must not be less than the specified receiver setup and hold time.  
The time periods specified in Figure 17 and Figure 18 on page 33 are defined by the transmitter speed. The receiver specifications  
must match transmitter performance.  
Document Number: 002-14943 Rev. *L  
Page 32 of 96  
 复制成功!