PRELIMINARY
CYW43340
UART timing is defined in Figure 16 and Table 13.
Figure 16. UART Timing
UART_CTS_N
UART_TXD
1
2
Midpoint of STOP bit
Midpoint of STOP bit
UART_RXD
3
UART_RTS_N
Table 13. UART Timing Specifications
Ref No. Characteristics
Minimum
Typical
Maximum
1.5
Unit
1
2
3
Delay time, UART_CTS_N low to UART_TXD valid
Setup time, UART_CTS_N high before midpoint of stop bit
Delay time, midpoint of stop bit to UART_RTS_N high
–
–
–
–
–
–
Bit periods
Bit periods
Bit periods
0.5
0.5
2
7.3 I S Interface
The CYW43340 supports an independent I2S digital audio port for high-fidelity Bluetooth audio. The I2S interface supports both master
and slave modes. The I2S signals are:
■ I2S clock: I2S SCK
■ I2S Word Select: I2S WS
■ I2S Data Out: I2S SDO
■ I2S Data In: I2S SDI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an output. The channel
word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the
I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling
edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high.
Data bits sent by the CYW43340 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the
rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider.
In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.
7.3.1 I2S Timing
Note: Timing values specified in Table 14 are relative to high and low threshold levels.
Document Number: 002-14943 Rev. *L
Page 31 of 96
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