PRELIMINARY
CYW43340
9. WLAN Host Interfaces
9.1 SDIO v2.0
The CYW43340 WLAN section supports SDIO version 2.0, including the following modes:
DS:
HS:
Default speed up to 25 MHz, including 1- and 4-bit modes (3.3V signaling)
High speed up to 50 MHz (3.3V signaling)
It also has the ability to map the interrupt signal onto a GPIO pin for applications requiring an interrupt different than what is provided
by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled
using the strapping option pins strap_host_ifc_[3:1].
Three functions are supported:
■ Function 0 standard SDIO function (Max BlockSize/ByteCount = 32B)
■ Function 1 backplane function to access the internal system-on-chip (SoC) address space (Max BlockSize/ByteCount = 64B)
■ Function 2 WLAN function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B)
9.1.1 SDIO Pin Descriptions
Table 16. SDIO Pin Description
SD 4-Bit Mode
Data line 0
SD 1-Bit Mode
DATA0
DATA1
DATA2
DATA3
CLK
DATA
IRQ
Data line
Interrupt
Data line 1 or Interrupt
Data line 2 or Read Wait
Data line 3
RW
Read Wait
Not used
Clock
N/C
Clock
CLK
CMD
CMD
Command line
Command line
Figure 20. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
CMD
SD Host
CYW43340
DAT[3:0]
Document Number: 002-14943 Rev. *L
Page 36 of 96
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