Table C-3. TCON Register - SRF 88h
Bit
Function
TCON.7
TF1 - Timer 1 overflow flag. Set to 1 when the Timer 1 count
overflows and cleared when the processor vectors to the
interrupt service routine.
TCON.6
TCON.5
TR1 - Timer 1 run control. Set to 1 to enable counting on
Timer 1.
TF0 - Timer 0 overflow flag. Set to 1 when the Timer 0 count
overflows and cleared when the processor vectors to the
interrupt service routine.
TCON.4
TCON.3
TR0 - Timer 0 run control. Set to 1 to enable counting on
Timer 0.
IE1 - Interrupt 1 edge detect. If external interrupt 1 is
configured to be edge-sensitive (IT1 = 1), IE1 is set by
hardware when a negative edge is detected on the INT1 pin
and is automatically cleared when the CPU vectors to the
corresponding interrupt service routine. In this case, IE1 can
also be cleared by software. If external interrupt 1 is
configured to be level-sensitive (IT1 = 0), IE1 is set when the
INT1# pin is 0 and cleared when the INT1# pin is 1. In level-
sensitive mode, software cannot write to IE1.
TCON.2
TCON.1
IT1 - Interrupt 1 type select. INT1 is detected on falling edge
when IT1 = 1; INT1 is detected as a low level when IT1 = 0.
IE0 - Interrupt 0 edge detect. If external interrupt 0 is
configured to be edge-sensitive (IT0 = 1), IE0 is set by
hardware when a negative edge is detected on the INT0 pin
and is automatically cleared when the CPU vectors to the
corresponding interrupt service routine. In this case, IE0 can
also be cleared by software. If external interrupt 0 is
configured to be level-sensitive (IT0 = 0), IE0 is set when the
INT0# pin is 0 and cleared when the INT0# pin is 1. In level-
sensitive mode, software cannot write to IE0.
TCON.0
IT0 - Interrupt 0 type select. INT0 is detected on falling edge
when IT0 = 1; INT0 is detected as a low level when IT0 = 0.
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 5
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