T0M
Divide by 12
Divide by 4
0
1
CLK24
CLK
0
1
C/T
7
TL0
0
T0 pin
TF0
TF1
INT
INT
TR0
GATE
TH0
INT0# pin
7
0
TR1
Figure C-3. Timer 0 - Mode 3
C.2.6 Mode 3
In mode 3, Timer 0 operates as two 8-bit counters and Timer 1 stops counting and holds its
value.
As shown in Figure C-3., TL0 is configured as an 8-bit counter controlled by the normal
Timer 0 control bits. TL0 can either count CLK24 cycles (divided by 4 or by 12) or high-to-
low transitions on T0, as determined by the C/T bit. The GATE function can be used to give
counter enable control to the INT0# pin.
TH0 functions as an independent 8-bit counter. However, TH0 can only count CLK24 cycles
(divided by 4 or by 12). The Timer 1 control and flag bits (TR1 and TF1) are used as the
control and flag bits for TH0.
When Timer 0 is in mode 3, Timer 1 has limited usage because Timer 0 uses the Timer 1
control bit (TR1) and interrupt flag (TF1). Timer 1 can still be used for baud rate generation
and the Timer 1 count values are still available in the TL1 and TH1 registers.
Control of Timer 1 when Timer 0 is in mode 3 is through the Timer 1 mode bits. To turn Timer
1 on, set Timer 1 to mode 0, 1, or 2. To turn Timer 1 off, set it to mode 3. The Timer 1 C/T bit
and T1M bit are still available to Timer 1. Therefore, Timer 1 can count CLK24/4,
CLK24/12, or high-to-low transitions on the T1 pin. The Timer 1 GATE function is also
available when Timer 0 is in mode 3.
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 7
CYPRESS [ CYPRESS ]
