Appendix C: 8051 Hardware Description
C.1
Introduction
This chapter provides technical data about the 8051 core hardware operation and timing. The
topics are:
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•
•
•
•
Timers/Counters
Serial Interface
Interrupts
Reset
Power Saving Modes
C.2
Timers/Counters
The 8051 core includes three timer/counters (Timer 0, Timer 1, and Timer 2). Each timer/
counter can operate as either a timer with a clock rate based on the CLK24 pin, or as an event
counter clocked by the T0 pin (Timer 0), T1 pin (Timer 1), or the T2 pin (Timer 2).
Each timer/counter consists of a 16-bit register that is accessible to software as two SFRs:
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•
•
Timer 0 - TL0 and TH0
Timer 1 - TL1 and TH1
Timer 2 - TL2 and TH2
EZ-USB TRM v1.9
Appendix C: 8051 Hardware Description
C - 1
CYPRESS [ CYPRESS ]
