C.2.7 Timer Rate Control
The default timer clock scheme for the 8051 timers is 12 CLK24 cycles per increment, the
same as in the standard 8051. However, in the 8051, the instruction cycle is 4 CLK24 cycles.
Using the default rate (12 clocks per timer increment) allows existing application code with
real-time dependencies, such as baud rate, to operate properly. However, applications that
require fast timing can set the timers to increment every 4 CLK24 cycles by setting bits in the
Clock Control register (CKCON) at SFR location 8Eh (see Table C-4.).
The CKCON bits that control the timer clock rates are:
CKCON BitCounter/Timer
5
4
3
Timer 2
Timer 1
Timer 0
When a CKCON register bit is set to 1, the associated counter increments at 4-CLK24
intervals. When a CKCON bit is cleared, the associated counter increments at 12-CLK24
intervals. The timer controls are independent of each other. The default setting for all three
timers is 0 (12-CLK24 intervals). These bits have no effect in counter mode.
Table C-4. CKCON Register - SRF 8Eh
Bit
Function
CKCON.7,6
CKCON.5
Reserved
T2M - Timer 2 clock select. When T2M = 0, Timer 2 uses
CLK24/12 (for compatibility with 80C32); when T2M = 1,
Timer 2 uses CLK24/4. This bit has no effect when Timer 2
is configured for baud rate generation.
CKCON.4
CKCON.3
CKCON.2-0
T1M - Timer 1 clock select. When T1M = 0, Timer 1 uses
CLK24/12 (for compatibility with 80C32); when T1M = 1,
Timer 1 uses CLK24/4.
T0M - Timer 0 clock select. When T0M = 0, Timer 0 uses
CLK24/12 (for compatibility with 80C32); when T0M = 1,
Timer 0 uses CLK24/4.
MD2, MD1, MD0 - Control the number of cycles to be used
for external MOVX instructions.
C - 8
Appendix C: 8051 Hardware Description
EZ-USB TRM v1.9
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