CY7C1351
Pin Definitions (continued)
Pin Number Name
83, 84 NC
I/O
Description
-
No Connects. Reserved for address inputs for depth expansion. Pins 83 and 84
will be used for 256K and 512K depths respectively.
38, 39, 42, 43 DNU
Introduction
-
Do Not Use pins. These pins should be left floating or tied to V
.
SS
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The CY7C1351 is a Synchronous Flow-Through Burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
rise (t
) is 11.0 ns (66-MHz device).
1
2
CDV
and CE are ALL asserted active, and (3) the write signal WE
3
Accesses can be initiated by asserting all three Chip Enables
(CE , CE , CE ) active at the rising edge of the clock. If Clock
is asserted LOW. The address presented to A –A is loaded
0
16
1
2
3
into the Address Register. The write signals are latched into
the Control Logic block. The data lines are automatically
three-stated regardless of the state of the OE input signal. This
Enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a Read or Write operation, depending on the
status of the Write Enable (WE). BWS
duct byte write operations.
allows the external logic to present the data on DQ
and
[31:0]
can be used to con-
[3:0]
DP
.
[3:0]
On the next clock rise the data presented to DQ
DP
and
[31:0]
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
(or a subset for byte write operations, see Write Cycle
[3:0]
Description table for details) inputs is latched into the device
and the write is complete. Additional accesses
(Read/Write/Deselect) can be initiated on this cycle.
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
The data written during the Write operation is controlled by
BWS
signals. The CY7C1351 provides byte write capabil-
[3:0]
ity that is described in the Write Cycle Description table. As-
serting the Write Enable input (WE) with the selected Byte
Write Select (BWS
) input will selectively write to only the
[3:0]
Single Read Accesses
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE
1
2
and CE are ALL asserted active, (3) the Write Enable input
3
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs (A –A
)
0
16
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the output buffers. The data is available
within 11.0 ns (66-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. On the subsequent clock, another operation
(Read/Write/Deselect) can be initiated. When the SRAM is de-
selected at clock rise by one of the chip enable signals, its
output will three-stated immediately.
Because the CY7C1351 is a common I/O device, Data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before present-
ing data to the DQ
and DP
inputs. Doing so will
[31:0]
[3:0]
three-state the output drivers. As a safety precaution, DQ
[31:0]
and DP
.are automatically three-stated during the data por-
[3:0]
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1351 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
Burst Read Accesses
The CY7C1351 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
the chip enables (CE , CE , and CE ) and WE inputs are ig-
1
2
3
nored and the burst counter is incremented. The correct
BWS inputs must be driven in each cycle of the burst write
[3:0]
in order to write the correct bytes of data.
4
CYPRESS [ CYPRESS ]
