CY7C1351
Interleaved Burst Sequence
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Write Cycle Description[1, 2]
Function
WE
1
BWS
X
1
BWS
X
1
BWS
X
1
BWS
X
1
3
2
1
0
Read
Write − No bytes written
0
Write Byte 0 − (DQ
Write Byte 1 – (DQ
Write Bytes 1, 0
Write Byte 2 − (DQ
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 − (DQ
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
and DP )
0
1
1
1
0
[7:0]
0
and DP )
0
1
1
0
1
[15:8]
1
0
1
1
0
0
and DP )
0
1
0
1
1
[23:16]
2
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
and DP )
0
0
1
1
1
[31:24]
3
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
6
CYPRESS [ CYPRESS ]
