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7C1351-66 参数 Datasheet PDF下载

7C1351-66图片预览
型号: 7C1351-66
PDF下载: 下载PDF文件 查看货源
内容描述: 128Kx36流通型SRAM与NOBL TM架构 [128Kx36 Flow-Through SRAM with NoBL TM Architecture]
分类和应用: 静态存储器
文件页数/大小: 13 页 / 185 K
品牌: CYPRESS [ CYPRESS ]
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CY7C1351  
[11, 12, 13]  
Switching Characteristics Over the Operating Range  
66  
50  
40  
Max.  
Parameter  
Description  
Min.  
Max.  
Min.  
20.0  
6.0  
Max.  
Min.  
25.0  
7.0  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock Cycle Time  
Clock HIGH  
15.0  
5.0  
5.0  
2.0  
0.5  
CYC  
CH  
Clock LOW  
6.0  
7.0  
CL  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
CEN Set-Up Before CLK Rise  
CEN Hold After CLK Rise  
2.0  
2.5  
AS  
1.0  
1.0  
AH  
11.0  
12.0  
14.0  
CDV  
DOH  
CENS  
CENH  
WES  
WEH  
ALS  
ALH  
DS  
1.5  
2.0  
0.5  
2.0  
0.5  
2.0  
0.5  
1.7  
0.5  
2.0  
0.5  
1.5  
2.0  
1.0  
2.0  
1.0  
2.0  
1.0  
2.0  
1.0  
2.0  
1.0  
1.5  
2.5  
1.0  
2.5  
1.0  
2.5  
1.0  
2.5  
1.0  
2.5  
1.0  
WE, BWS  
WE, BWS  
Set-Up Before CLK Rise  
Hold After CLK Rise  
[3:0]  
[3:0]  
ADV/LD Set-Up Before CLK Rise  
ADV/LD Hold after CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
DH  
CES  
CEH  
CHZ  
CLZ  
EOHZ  
EOLZ  
EOV  
Chip Select Hold After CLK Rise  
[10, 12, 13, 14]  
Clock to High-Z  
5.0  
6.0  
6.0  
5.0  
7.0  
7.0  
5.0  
8.0  
8.0  
[10, 12, 13, 14]  
Clock to Low-Z  
3.0  
0
3.0  
0
3.0  
0
[10, 12, 13, 14]  
OE HIGH to Output High-Z  
[10, 12, 13, 14]  
OE LOW to Output Low-Z  
[12]  
OE LOW to Output Valid  
Notes:  
11. Unless otherwise noted, test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading shown in (a) of AC Test Loads.  
12.  
tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state  
voltage.  
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
14. This parameter is sampled and not 100% tested.  
9
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