CY7C1351
.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Address
used
ADV/
LD
Operation
CE
CEN
WE
BWS
CLK
Comments
x
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next
recognized clock.
Suspend
-
X
1
X
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
Begin Write
External
External
0
0
0
0
0
0
1
0
L-H
L-H
Address latched.
Valid
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS
.
[3:0]
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS
x
x
= Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS
. See Write Cycle Description table for details.
[3:0]
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
5
CYPRESS [ CYPRESS ]
