CX82100 Home Network Processor Data Sheet
13.4.3
Low Power Mode Register (LPMR: 0x00350014)
Bit(s)
31:16
Type
RW
Default
16'b0
Name
LPM_CLK_DIV
Description
Low Power Mode Clock Divider.
In Low Power Mode, BCLK operation is changed to:
BCLK = CLKI/(LPM_CLK_DIV + 1)*2
For example, a BCLK as slow as 270 Hz can be generated using a
35.328 MHz CLKI as the input if Low Power Mode is enabled
(LPM_EN = 1) and BCLK slow speed is not selected
(PLL_B_CR_SLOW = 0 in the PLL_B register).
If both LPM_EN and PLL_B_CR_SLOW = 1, the clock frequency for
BCLK is additionally divided by 2.
Reserved.
Low Power Mode Enable.
0 = Normal mode.
15:1
0
RW
0
LPM_EN
1 = Enable Low Power Mode, i.e., BCLK operates as described in
LPMR[31:16]. It also switches off FCLK and UCLK to the
ARM40T Core and USB Block.
Note: This control bit will not switch off or power-down the PLLs. To
put the PLLs in a power-down state, the PLL_F_INT / PLL_B_INT
values (bits [21:16] in PLL_F and PLL_B registers) must be 0.
101306C
Conexant Proprietary and Confidential Information
13-7
CONEXANT [ CONEXANT SYSTEMS, INC ]
