CX82100 Home Network Processor Data Sheet
13.5
PLL Programming
The PLL output frequency synthesized is equal to:
æ
ö
÷
÷
ø
CLKI _ Freq(MHz)
PLL _{X}_ PRE
PLL _{X}_ FRAC
ç
PLL _ Output _ Freq
(
MHz
)
=
× PLL _{X}_ INT +
÷ 2
216
ç
è
where X refers to F or B for the FCLK and BCLK PLLs, respectively.
For proper operation, FCLK must always be equal or greater than BCLK.
The divide ratio for each desired clock frequency is given by:
Desired_ Freq
(
MHz
)
×2× PLL_{X}_ PRE
PLL_{X}_ FRAC
Divide_ Ratio=
= PLL_{X}_ INT +
16
CLKI_ Freq(MHz)
2
At power-up and reset, both FCLK and BCLK and default to 48 MHz and 25 MHz,
respectively, when using a 35.328 MHz CLKI input.
Table 13-8 shows some desired frequencies and the necessary parameters for
programming the PLL_F and the PLL_B registers (assuming a 35.328 MHz input at
CLKI.
Table 13-8. Desired Frequencies and Programming Parameters
Example
CLKI
Frequency
(MHz)
PreScaler
Desired
Frequency
(MHz)
Divide
Ratio
Integer
(Dec.)
Fraction
(Dec.)
PLL Output
Frequency
(MHz)
PLL_Register
1
2
3
4
5
6
35.328
35.328
35.328
35.328
35.328
35.328
5
3
4
3
3
3
75
96
100
120
144
168
21.229620
16.304348
22.644928
20.380435
24.456522
28.532608
21
16
22
20
24
28
15048
19946
42266
24932
29919
34905
74.99998125
96.00002344
100.000002
119.9999844
144.0000352
167.9999960
0x00553AC8
0x00D04DEA
0x0196A51A
0x01D46164
0x02D874DF
0x03DC8859
13-8
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CONEXANT [ CONEXANT SYSTEMS, INC ]
