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CX82100-52 参数 Datasheet PDF下载

CX82100-52图片预览
型号: CX82100-52
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭网络处理器( HNP ) [Home Network Processor (HNP)]
分类和应用:
文件页数/大小: 226 页 / 1406 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX82100 Home Network Processor Data Sheet  
Table 13-3. FCLK PLL Generated Clocks  
Clock  
Minimum  
Frequency  
(MHz)  
Maximum  
Operating  
Frequency  
(MHz)  
Description  
FCLK  
96  
48  
168  
ARM940T fast clock input, asynchronous to bus clock. Can have a lower minimum if  
the USB interface is not used. Internal. FCLK must be equal to or greater than BCLK.  
UCLK  
84  
USB timing reference; always one-half the frequency of FCLK. Must be a multiple of  
12 MHz for proper USB operation. Internal. Optionally external, output on FCLKIO  
pin.  
UDC  
12  
12  
USB timing reference. Must be 12 MHz for proper USB operation; UCLK divided by  
number corresponding to PLL_F_CR. Internal.  
Table 13-4. BCLK PLL Generated Clocks  
Clock  
Minimum  
Frequency  
(MHz)  
Maximum  
Operating  
Frequency  
(MHz)  
Description  
BCLK  
PCLK  
25  
12.5  
100  
50  
ASB clock. Internal. Can have a lower minimum if EPCLK is not used for 25 MHz.  
APB clock; always one-half the frequency of BCLK and aligned to BCLK falling edge.  
Internal.  
EPCLK  
25  
25  
Miscellaneous timing reference, e.g., Ethernet PHY. Optionally external; output on  
BCLKIO pin. Can be different frequency for applications other than an Ethernet PHY  
clock.  
Table 13-5. FCLK PLL Generated Clocks Programming Examples  
FCLK Speed Select  
(PLL_F_CR_SLOW)  
PLL_F  
FCLK (ARM)  
Frequency  
UCLK  
USB Clock  
Rate Select  
(PLL_F_CR)  
UDC Clock  
Frequency  
Notes  
Frequency  
Frequency  
(FCLK/2)  
0 (Normal)  
0 (Normal)  
0 (Normal)  
0 (Normal)  
1 (Slow)  
1 (Slow)  
1 (Slow)  
1 (Slow)  
96 MHz  
120 MHz  
144 MHz  
168 MHz  
96 MHz  
120 MHz  
144 MHz  
168 MHz  
96 MHz  
120 MHz  
144 MHz  
168 MHz  
48 MHz  
60 MHz  
72 MHz  
84 MHz  
48 MHz  
60 MHz  
72 MHz  
84 MHz  
48 MHz  
60 MHz  
72 MHz  
84 MHz  
12 MHz  
12 MHz  
12 MHz  
12 MHz  
12 MHz  
12 MHz  
12 MHz  
12 MHz  
00 (÷ 8)  
01 (÷ 10)  
10 (÷ 12)  
10 (÷ 14)  
00 (÷ 4)  
01 (÷ 5)  
10 (÷ 6)  
10 (÷ 7)  
Default at POR  
Table 13-6. BCLK PLL Generated Clocks Programming Examples  
BCLK Speed Select  
(PLL_F_CR_SLOW)  
PLL_B  
BCLK (ASB)  
Frequency  
PCLK (APB)  
Frequency  
(BCLK/2)  
EPCLK Clock  
Rate Select  
(PLL_B_CR)  
EPCLK  
(XBCLK)  
Clock  
Notes  
Frequency  
Frequency  
0 (Normal)  
0 (Normal)  
1 (Slow)  
75 MHz  
100 MHz  
50 MHz  
75 MHz  
100 MHz  
25 MHz  
50 MHz  
37.5 MHz  
50 MHz  
12.5MHz  
25 MHz  
25 MHz  
25 MHz  
25 MHz  
25 MHz  
00 (÷ 3)  
01 (÷ 4)  
00 (÷ 1)  
01 (÷ 2)  
Default at POR  
1 (Slow)  
100 MHz  
13-4  
Conexant Proprietary and Confidential Information  
101306C  
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