CX82100 Home Network Processor Data Sheet
13.4.2
BCLK PLL Register (PLL_B: 0x0035006C)
PLL_B register is used by the BCLK PLL to generated the desired clocks
BCLK/PCLK/EPCLK.
Bit(s)
31:29
28
Type
Default
Name
Description
Reserved.
BCLK Slow Speed Select.
0 = Normal BCLK speed.
RW
1’b1
PLL_B_CR_SLOW
1 = Slow BCLK speed (one-half normal speed). (Default)
BCLK PLL Lock Status.
27
26
RO
RW
1’b1
1’b0
PLL_B_LK
0 = BCLK PLL not locked.
1 = BCLK PLL locked (must be continuous 1 to indicate proper
BCLK PLL operation).
PLL_B_DDS
Disable BCLK ∆Σ Synthesizer.
0 = Enable BCLK ∆Σ synthesizer and select fractional divides.
(Default)
1 = Disable the BCLK ∆Σ synthesizer and select integer-only
divides.
25:24
RW
2’b00
PLL_B_CR
EPCLK Clock Rate Select Divider.
For PLL_B_CR_SLOW = 0:
00 = BCLK divided by 3.
01 = BCLK divided by 4.
10 = BCLK divided by 5.
For PLL_B_CR_SLOW = 1:
00 = BCLK divided by 1. (Default)
01 = BCLK divided by 2.
10 = Reserved.
23:22
RW
2’b01
PLL_B_PRE
BCLK Reference Input Prescale Divider Select.
00 = Reserved.
01 = Divide by 5. (Default)
10 = Divide by 4.
11 = Divide by 3.
BCLK 6-bit Integer Divide Select.
21:16
15:0
RW
RW
6’b001110
(14d)
PLL_B_INT
0 =
Selects PLL power-down state.
≥ 14d Enables the PLL for normal operation as a clock synthesizer.
See 13.5. (Default)
16’h2730
(10032d)
PLL_B_FRAC
BCLK 16-bit Fractional Divide.
See 13.5.
13-6
Conexant Proprietary and Confidential Information
101306C