CX82100 Home Network Processor Data Sheet
12
Timers Interface Description
12.1
Programmable Periodic Timers
There are four programmable timers (Timer 1—Timer 4) available for real-time
interrupts with a normal range from 1 µs to 65 ms. Timer 3 can also be used as a system
watchdog timer.
The timers are based on 16-bit counters that increment at a 1.0 MHz rate. The 1.0 MHz
rate is based upon PCLK and PLL_B register bits PLL_B_CR. Table 13-6 shows the
BCLK clock frequencies for which the 1.0 MHz rate is guaranteed. If the PLL_B
frequency is not programmed to the listed values, the timers will not run at 1.0 MHz. See
Section 12 for more information.
Each timer’s counter register (TM_Cnt{x}) is reset to 0 when its limit register
(TM_Lmt{x}) is written. Each timer’s TM_Cnt register increments from 0 up to the limit
value programmed in its TM_Lmt register. When the counter reaches the limit value, the
counter resets back to 0 and sets its corresponding interrupt status bit (Int_TIMER{x} –
see Section 11.2.2). An interrupt to the ARM940T processor will then occur if the
corresponding interrupt enable bit is set in the Interrupt Mask Register (INT_Msk[3:0].
The counters continue to increment during the pending interrupts. If TM_Lmt{x} is set to
0, TM_Cnt{x} stays reset, does not increment, and therefore never causes an interrupt.
As an example, a 50 ms periodic real-time interrupt can be achieved by setting
TM_Lmt{x} to 16’hC34F.
12.2
Watchdog Timer
A system watchdog is implemented via a special case of Timer 3. The timer counts up to
TM_Lmt3. When reached it sets the Int_TM3 interrupt. This normal operation, like the
other two timers, produces an Int_TM3 interrupt every (1 + TM_Lmt3) µs.
Unlike the other timers, if TM_Lmt3[3:0] is written with a value of 1’hF, watchdog mode
is enabled. This particular nibble of TM_Lmt3 causes TM_Lmt3 to not be able to be
changed (i.e., writes will have no effect) until after the next system reset. It also causes an
internal 7-bit counter to increment after every Int_TIMER3 event. If this counter is not
cleared by writing TM_Lmt3 with any value (this does not affect TM_Lmt3 after initial
programming) before the 7-bit counter reaches 100, a global reset will take effect, which
is the same in effect as asserting the HRST# pin.
The watchdog function is “re-armed” after each clear, i.e., the 7-bit counter is reset to 0
after each write to TM_Lmt3. Once enabled, it cannot be disabled other than by a global
reset.
For example, if TM_Lmt3 is programmed to 16’h61A7, then a normal Int_TIMER3
interrupt occurs every 25 ms and the watchdog function is not enabled. If TM_Lmt3 is
programmed to 16’h270F, then an Int_TIMER3 interrupt occurs every 10 ms and the
watchdog function of Timer 3 is enabled. The 7-bit counter must be cleared by writing to
TM_Lmt3 before a timeout of 1 sec occurs, otherwise the global reset will occur.
101306C
Conexant Proprietary and Confidential Information
12-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
