CX82100 Home Network Processor Data Sheet
11.2.2
Interrupt Status Register (INT_Stat: 0x00350044)
Each interrupt source sets a bit in the interrupt status register (INT_Stat). These pending
interrupts can be read at anytime. If a bit in this register represents multiple interrupt
sources, then it is read-only. Most bits are automatically cleared once all the
corresponding interrupt sources are cleared, however, bits 19 and 20 are not
automatically cleared. Any other bit in this register can be cleared by writing a one to the
same bit location. (Note that in some cases, the interrupt source in the peripheral must be
cleared before the clearing of the corresponding interrupt bit in this register can take
effect.).
Writing a zero has no effect.
Bit
Type
Default
Name
Description
31
RR
1’b0
Int_SW3
Int_SW2
Int_SW1
Int_SW0
Software Interrupt 3.
0 = Interrupt condition has not occurred.
1 = The corresponding data bit has been set high when writing
to INT_SetStat.
Software Interrupt 2.
30
29
28
27
RR
RR
RR
RR
1’b0
1’b0
1’b0
1’b0
0 = Interrupt condition has not occurred.
1 = The corresponding data bit has been set high when writing
to INT_SetStat.
Software Interrupt 1.
0 = Interrupt condition has not occurred.
1 = The corresponding data bit has been set high when writing
to INT_SetStat.
Software Interrupt 0.
0 = Interrupt condition has not occurred.
1 = The corresponding data bit has been set high when writing
to INT_SetStat.
Int_COMMRX
ARM9 Communication RXD Channel Interrupt.
0 = The receive buffer does not contain data waiting to be
read.
1 = The ARM9 communication RXD channel (between
processor and the debugger) receive buffer contains data
waiting to be read.
26
RR
RO
1’b0
1’b0
Int_COMMTX
Int_GPIO
ARM9 Communication TXD channel Interrupt.
0 = The transmit buffer is not empty.
1 = The ARM9 communication TXD channel (between
processor and the debugger) transmit buffer is empty.
25
24
Reserved.
GPIO Interrupt.
0 = Interrupt condition has not occurred.
1 = An external interrupt through a GPIO input pin has
occurred.
23:21
20
Reserved.
RR
RR
1’b0
1’b0
Int_EMAC#2_ERR
Int_EMAC#1_ERR
EMAC 2 Exception Condition Interrupt.
0 = Interrupt condition has not occurred.
1 = EMAC 2 receiver or transmitter detected a normal or
abnormal exception condition. Must be written to be
cleared.
EMAC 1 Exception Condition Interrupt.
0 = Interrupt condition has not occurred.
19
1 = EMAC 1 receiver or transmitter detected a normal or
abnormal exception condition. Must be written to be
cleared.
11-2
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