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CX82100-52 参数 Datasheet PDF下载

CX82100-52图片预览
型号: CX82100-52
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭网络处理器( HNP ) [Home Network Processor (HNP)]
分类和应用:
文件页数/大小: 226 页 / 1406 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX82100 Home Network Processor Data Sheet  
12.3  
Timer Usage/SDRAM Refresh with Other Frequencies  
Normal HNP operation assumes BCLK is 25, 50, 62.5, 75, or 100 MHz (see Section  
13.1). The timer resolution circuitry and SDRAM refresh rates are based upon these  
frequencies. However, if a different frequency is desired, the resolution of the timer and  
SDRAM refresh rates are based on parameter values listed in Table 12-1.  
Table 12-1. Timer Resolution and SDRAM Refresh Rate  
BCLK Speed Select  
(PLL_B_CR_SLOW)  
EPCLK Clock  
Rate Select  
(PLL_B_CR)  
Resolution  
SDRAM  
Notes  
Refresh Rate  
0 (Normal)  
0 (Normal)  
0 (Normal)  
1 (Slow)  
PCLK/37.5  
PCLK/50  
PCLK/62.5  
PCLK/12.5  
PCLK/25  
BCLK/900  
BCLK/1200  
BCLK/1500  
BCLK/300  
BCLK/600  
00 (÷ 3)  
01 (÷ 4)  
10 (÷ 5)  
00 (÷ 1)  
01 (÷ 2)  
Default at POR  
1 (Slow)  
SDRAMs typically require refresh rates at approximately 15.6 µs or faster. Normal HNP  
operation, when configuring BCLK as in Section 13.1, achieves a refresh rate of 12 µs.  
Care must be taken to avoid use of a refresh rate that is too slow. If the refresh rate is too  
fast, application performance could be reduced.  
A normal example is that BCLK is programmed for 100 MHz, with PLL_B_CR_SLOW  
= 0 and PLL_B_CR = 01. PCLK would then be 50 MHz, EPCLK would then be 25  
MHz, and the timer resolution would be 50/50 MHz, which is equal to 1 µs. The SDRAM  
refresh rate would be 100 MHz/1200, which is equal to 12 µs.  
An example using a different BCLK frequency is BCLK programmed to be 80 MHz,  
with PLL_B_CR_SLOW = 0 and PLL_B_CR = 01. PCLK would then be 40 MHz,  
EPCLK would then be 20 MHz, and the timer resolution would be 40 MHz/50, which is  
equal to 1.25 µs. The SDRAM refresh rate would be 80 MHz/1200, which is equal to  
15 µs.  
Another example using a different BCLK frequency is BCLK programmed to be 40  
MHz, with PLL_B_CR_SLOW = 1 (default) and PLL_B_CR = 00 (default). PCLK  
would then be 20 MHz, EPCLK would then be 40 MHz, and the timer resolution would  
be 20 MHz/12.5 which is equal to 0.625 µs. The SDRAM refresh rate would be 40  
MHz/300, which is equal to 7.5 µs.  
12-2  
Conexant Proprietary and Confidential Information  
101306C  
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