CX82100 Home Network Processor Data Sheet
11.2.3
Interrupt Set Status Register (INT_SetStat: 0x00350048)
This is a Write-Only register. The interrupt set status (INT_SetStat) register has 32 bits.
Writing a one to a bit location of this register will cause the corresponding interrupt to
occur. Writing a zero will have no effect. Only the four software interrupts defined in
INT_Stat[31:28] can be triggered by using this register.
Bit
31:28
Type
WO
Default
4’b0
Name
Int_SetStat_x
Description
Interrupt Set Status Control.
0 = No effect.
1 = Forces an interrupt to the INTC if the corresponding bit location in
the INT_Msk register is enabled. Will cause the corresponding bit
in the INT_Stat register to be set.
27:0
Reserved.
11.2.4
Interrupt Mask Register (INT_Msk: 0x0035004C)
The pending interrupts are masked (ANDed) with the interrupt mask register (INT_Msk)
before being logically ORed to the ARM interrupt input. The INT_Msk register has 32
bits. Writing a one to a bit location of this register will enable the corresponding interrupt
in INT_Stat. Writing a zero to a bit location of this register will disable the interrupt. The
enabled or active interrupts are also readable at register INT_Mstat.
Bit
31:0
Type
RW
Default
32’h00000000
Name
Int_MSK_x
Description
Interrupt Mask (Enable) Control.
0 = Interrupts on the corresponding bit location in the INT_Stat
register are disabled.
1 = Interrupts on the corresponding bit location in the INT_Stat
register are enabled.
11.2.5
Interrupt Mask Status Register (INT_Mstat: 0x00350090)
This is a Read-Only register. It is logically equivalent to the AND of INT_Stat and
INT_Msk registers. It provides a convenient way for software to determine which
interrupts have occurred.
Bit
31:0
Type
RO
Default
32’h00000000
Name
Int_Mstat_x
Description
Interrupt Mask Status.
0 = Interrupts has not occurred on the corresponding bit location in
the INT_Stat register.
1 = Interrupts has occurred on the corresponding bit location in the
INT_Stat register.
11-4
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