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CX82100-52 参数 Datasheet PDF下载

CX82100-52图片预览
型号: CX82100-52
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭网络处理器( HNP ) [Home Network Processor (HNP)]
分类和应用:
文件页数/大小: 226 页 / 1406 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX82100 Home Network Processor Data Sheet  
11  
Interrupt Controller Interface Description  
All peripheral interrupt sources are routed through the Interrupt Controller (INTC) and  
reduced to one of two active low inputs to the ARM940T processor, fast interrupt (FIQ#)  
or regular interrupt (IRQ#), as selected in the Interrupt Level Assignment Register  
(INT_LA). No hardware-assisted priority scheme is implemented in the HNP other than  
FIQ# having a higher priority than IRQ#. The system software must implement the  
priority scheme for individual interrupts in the FIQ# and IRQ# exception handlers.  
11.1  
INTC Register Memory Map  
INTC registers are identified in Table 11-1.  
Table 11-1. INTC Registers  
Register Label  
INT_LA  
INT_Stat  
INT_SetStat  
INT_Msk  
INT_Mstat  
Register Name  
Interrupt Level Assignment Register  
Interrupt Status Register  
Interrupt Set Status Register  
Interrupt Mask Register  
ASB Address  
0x00350040  
0x00350044  
0x00350048  
0x0035004C  
0x00350090  
Type  
RW  
RR  
WO  
RW  
RO  
Default Value  
0x00000000  
0x00000000  
0x00000000  
0x00000000  
0x00000000  
Ref.  
11.2.1  
11.2.2  
11.2.3  
11.2.4  
11.2.5  
Interrupt Mask Status Register  
11.2  
INTC Registers  
11.2.1  
Interrupt Level Assignment Register (INT_LA: 0x00350040)  
The INTC receives an interrupt signal from a potential interrupt source and compares it  
with the corresponding interrupt level assignment register (INT_LA) to determine if a  
fast interrupt (FIQ#) signal or a regular interrupt (IRQ#) signal should be sent to the  
ARM940T processor. Setting the interrupt's corresponding bit on the Interrupt Level  
Assignment Register to a 1 will cause a FIQ# interrupt, while a 0 will cause an IRQ#  
interrupt.  
Bit  
31:0  
Type  
RW  
Default  
32’h00000000  
Name  
Int_LA_x  
Description  
Level Assignment Interrupt Control.  
0 = The corresponding bit location in the INT_Stat register will cause  
an IRQ# interrupt to the INTC if the interrupt has been enabled.  
1 = The corresponding bit location in the INT_Stat register will cause  
a FIQ# interrupt to the INTC if the interrupt has been enabled.  
101306C  
Conexant Proprietary and Confidential Information  
11-1  
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