CX82100 Home Network Processor Data Sheet
Table 10-2. M2M Transfer Example 2
M2M Data Transfer Example
Byte
Source Memory
to Copy: 24B
Destination
Memory before
Copy
Destination Memory after Copy
Address
M2M_Cnt = 3 qwords, DMA8_Ptr1 = 00
Start Destination Byte-Address
Start Source
Byte-Address
1
0
1
2
3
M2M_BS, DMA7_Ptr1
3, 04
0, 00
1, 00
2, 00
00
04
08
0C
10
14
18
03020100
07060504
0B0A0908
0F0E0D0C
13121110
17161514
1B1A1918
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
04xxxxxx
08070605
0C0B0A09
100F0E0D
14131211
18171615
FFFFFFFF
03020100
07060504
0B0A0908
0F0E0D0C
13121110
17161514
FFFFFFFF
020100xx
06050403
0A090807
0E0D0C0B
1211100F
16151413
FFFFFFFF
0100xxxx
05040302
09080706
0D0C0B0A
11100F0E
15141312
FFFFFFFF
Table 10-3. M2M Transfer Example 3
M2M Data Transfer Example
Byte
Source Memory
to Copy: 24B
Destination
Memory before
Copy
Destination Memory after Copy
Address
M2M_Cnt = 3 qwords, DMA8_Ptr1 = 00
Start Source
Start Destination Byte-Address
Byte-Address
3
0
1
2
3
M2M_BS, DMA7_Ptr1
1, 04
2, 04
3, 04
0, 00
00
04
08
0C
10
14
18
03020100
07060504
0B0A0908
0F0E0D0C
13121110
17161514
1B1A1918
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
060504xx
0A090807
0E0D0C0B
1211100F
16151413
1A191817
FFFFFFFF
0504xxxx
09080706
0D0C0B0A
11100F0E
15141312
19181716
FFFFFFFF
04xxxxxx
08070605
0C0B0A09
100F0E0D
14131211
18171615
FFFFFFFF
03020100
07060504
0B0A0908
0F0E0D0C
13121110
17161514
FFFFFFFF
When doing a multiple qword buffer transfer there are actually 128 cases to consider for
byte re-alignment. This # of permutations results from 4 start byte src-locations, 8 end
byte src-locations, and 4 start byte dst-locations (4x8x4 = 128). The start/end src-
locations bound the buffer size for transfer. The firmware will need to fix the corrupted
first dword (save original dst-1st-loc before copy), and also supply the last byte-merged 1-
2 dwords.
10-2
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