CX82100 Home Network Processor Data Sheet
10.2
M2M Register Memory Map
M2M registers are identified in Table 10-4
Table 10-4. M2M Registers
Register Label
M2M_DMA
M2M_Cntl
Register Name
ASB Address
0x00350000
0x00350004
Type
RWp
RW
Default Value
64’bx
0x00000000
Ref.
10.3.1
10.3.2
Memory to Memory DMA Data Register
Memory to Memory DMA Transfer
Control/Counter
10.3
M2M Registers
10.3.1
Memory to Memory DMA Data Register (M2M_DMA: 0x00350000)
Bit(s)
63:0
Type
RWp
Default
64’bx
Name
M2M_DMA
Description
A single qword buffer for DMA source/destination access.
10.3.2
Memory to Memory DMA Transfer Control/Counter (M2M_Cntl: 0x00350004)
Bit(s)
22:21
Type
RW
Default
2’b0
Name
Description
M2M_BS
M2M_DO
Memory to Memory Bytes to Lag Data or Shift Left.
No. of bytes to lag data or shift left. Useful for little-endian
byte re-alignment.
20
RW
RW
1’b0
Disabled Memory to Memory Source Transfers.
0 = Enable source and destination transfers.
1 = Disable source transfers, and enable only
destination transfers.
19:0
20’b0
M2M_Cnt
Memory to Memory Count.
No. of qwords to transfer.
101306C
Conexant Proprietary and Confidential Information
10-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
