CX82100 Home Network Processor Data Sheet
10
Memory to Memory Transfer Input/Output
10.1
Operation
A qword buffer resides within this block to support memory to memory block transfers.
Data transfer requests are issued to the DMAC via channel 7 for reading from the source
buffer and channel 8 for writing to the destination buffer. The number of qwords to
transfer is set by M2M_Cntl. This count is big enough to initialize the entire 8 MB of
external SDRAM if desired. When M2M_Cntl is set to 0, or counts down to 0, the DMA
block transfer is done. An interrupt is set (INT_Stat:8) when the DMAC completes the
data block transfer. If M2M_DO is set, then only write transfers will occur to the
destination buffer. Since the ARM can also write to the DMA port buffer M2M_DMA, it
could use the DMAC to initialize memory to any constant.
The memory-to-memory transfer always consists of an integer number of qwords. The
source and destination addresses are always dword-aligned. Little-endian byte-
realignment is supported by using M2M_BS and using firmware for cleaning up the end
conditions. Some examples for M2M data transfers are shown in Table 10-1, Table 10-2,
and Table 10-3. The bytes highlighted in bold have to be copied or restored by firmware.
Table 10-1. M2M Transfer Example 1
M2M Data Transfer Example
Destination Memory after Copy
Byte
Source Memory
to Copy: 24B
Destination
Memory before
Copy
Address
M2M_Cnt = 3 qwords, DMA8_Ptr1 = 00
Start Destination Byte-Address
Start Source
Byte-Address
0
0
1
2
3
M2M_BS, DMA7_Ptr1
0, 00
1, 00
2, 00
3, 00
00
04
08
0C
10
14
18
03020100
07060504
0B0A0908
0F0E0D0C
13121110
17161514
1B1A1918
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
03020100
07060504
0B0A0908
0F0E0D0C
13121110
17161514
FFFFFFFF
020100xx
06050403
0A090807
0E0D0C0B
1211100F
16151413
FFFFFFFF
0100xxxx
05040302
09080706
0D0C0B0A
11100F0E
15141312
FFFFFFFF
00xxxxxx
04030201
08070605
0C0B0A09
100F0E0D
14131211
FFFFFFFF
101306C
Conexant Proprietary and Confidential Information
10-1