CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.16 System Bus Registers
0D9—Slip Buffer Status (SSTAT)
SSTAT[7:0] are updated at the start of each respective receive/transmit internal frame boundary (i.e. 125 µs
interval). Each bit in SSTAT is latched upon event detection and held until read cleared by the processor.
7
6
5
4
3
2
1
0
TSDIR
TFSLIP
TUSLIP
TDLY
RSDIR
RFSLIP
RUSLIP
RDLY
TSDIR
Transmit Slip Direction—TSDIR is updated each time a TSLIP error is latched in TFSLIP and
TSDIR indicates which direction the slip occurred.
0 = TSLIP error deleted 1 frame on TX data output
1 = TSLIP error repeated 1 frame on TX data output
TFSLIP
Controlled TSLIP Event—TUSLIP and TFSLIP event status are latched active high when
transmit slip error is detected. Either event reports a TSLIP error in ISR5 [addr 006]. Active
high hold interval is defined by LATCH_ERR [addr 046].
Two types of errors are detected:
1. FSLIP = Controlled ± frame slip on TX data output. FSLIP affects transmit
time slot data, but does not change transmit timebase or frame alignment.
2. USLIP = Uncontrolled ± 1 to ± 256 bit slip on TX data. USLIP affects both
time slot data and frame alignment. TUSLIP and TFSLIP status depends
on transmit system bus configuration [TSB_CR; addr 0D4].
TSBI Mode
Normal
TUSLIP
TFSLIP
TSLIP Event
0
0
0
1
None
FSLIP
1
0
USLIP
1(1)
1
Both FSLIP and USLIP
Short
0
0
None
FSLIP
USLIP
None
USLIP
—
0
1
1
0
Elastic
Bypass
0
n/a
n/a
n/a
1
n/a
NOTE(S):
(1)
Most recent slip error direction is reported in TSDIR.
2. TFSLIP not applicable (read zero value) if TSLIP is bypassed or configured as elastic store.
TUSLIP not applicable if TSLIP bypassed. In short delay mode, if the bus clock is faster than the
receive clock, the system bus will resynchronize and USLIP is reported. If the receive clock is
faster, RSLIP reverts to normal mode and subsequently reports FSLIP errors.
TUSLIP
TDLY
Uncontrolled TSLIP Event—See TFSLIP description.
Transmit Slip Buffer Delay > One Frame—Indicates that real-time phase difference between
TSLIP read and write pointers is more than 192 bits (T1) or 256 bits (E1). TDLY provides a
coarse phase indicator and toggles (low) if transmit system bus clock phase advances with
respect to the transmit line rate clock. A finer granularity of TSLIP phase is reported in
TPHASE [addr 0DC].
0 = TSLIP delay less than or equal to 1 frame
1 = TSLIP delay greater than 1 frame
100054E
Conexant
3-105
CONEXANT [ CONEXANT SYSTEMS, INC ]
