3.0 Registers
CX28394/28395/28398
3.16 System Bus Registers
Quad/x16/Octal—T1/E1/J1 Framers
0DB—RSLIP Phase Status (RPHASE)
7
6
5
4
3
2
1
0
RDELAY[5]
RDELAY[4]
RDELAY[3]
RDELAY[2]
RDELAY[1]
RDELAY[0]
RSLIP_WR
RSLIP_RD
RDELAY[5:0]
RSLIP Buffer Delay—Difference between RX and RSB timebase in time slot intervals.
Reported once per frame coincident with RFRAME interrupt [ISR3; addr 008]. Actual delay
may vary significantly, depending on which time slots are assigned.
000000 = RX to RSB delay in the range of 0–7 bits
|
111111 = RX to RSB delay in the range of 504–511 bits
RSLIP_WR
RSLIP_RD
Active RSB Slip Buffer Half—This bit indicates which half of the receive slip buffer is
currently supplying data to the Receive System Bus (0 = RLIP_LO, 1 = RSLIP_HI). The
processor can write data to the opposite buffer half.
Active Receiver Slip Buffer Half—This bit indicates which half of the receive slip buffer is
currently receiving data from the receiver (0 = RSLIP_LO, 1 = RSLIP_HI). The processor can
read data from the opposite buffer half.
0DC—TSLIP Phase Status (TPHASE)
7
6
5
4
3
2
1
0
TDELAY[5]
TDELAY[4]
TDELAY[3]
TDELAY[2]
TDELAY[1]
TDELAY[0]
TSLIP_WR
TSLIP_RD
TDELAY[5:0]
TSLIP Buffer Delay—Difference between TSB and TX timebase in time slot intervals.
Reported once per frame coincident with TFRAME interrupt [ISR3; addr 008]. The actual
delay may vary significantly, depending on which time slots are assigned.
000000 = TSB to TX delay in the range of 0–7 bits
|
111111 = TSB to TX delay in the range of 496–503 bits
TSLIP_WR
TSLIP_RD
Active Transmitter Slip Buffer Half—This bit indicates which half of the transmit slip buffer is
currently supplying data to the transmitter (0 = TSLIP_LO, 1 = TSLIP_HI). The processor can
write data to the opposite buffer half.
Active TSB Slip Buffer Half—This bit indicates which half of the transmit slip buffer is
currently receiving data from the Transmit System Bus (0 = TSLIP_LO, 1 = TSLIP_HI). The
processor can read data from the opposite buffer half.
3-108
Conexant
100054E