CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.16 System Bus Registers
0D6—TSB Sync Time Slot Offset (TSYNC_TS)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
OFFSET[9]
OFFSET[8]
OFFSET[7]
OFFSET[6]
OFFSET[5]
OFFSET[4]
OFFSET[3]
OFFSET[9:3]
TSB Sync Time Slot Offset—Selects which TSB time slot number coincides with TFSYNC
and TMSYNC sync pulses, in the range of Time Slots 0 through 127. If the sync pulses
coincide with location of T1 F-bit or TS0, then OFFSET is programmed to equal zero. Refer
also to TSYNC_TS [addr 0D6].
2048, 1544, and 1536 Kbps/sec SBI Mode
OFFSET[9:3]
0000000
0000001
|
TSYNC Time Slot
0 or F-bit
1
|
0011110
0011111
30
31
4096 Kbps/sec SBI Mode
OFFSET[9:4]
OFFSET[3]
TSYNC Time
Slot
Group
000000
000000
000001
000001
|
0
1
0
1
|
0
0
A
B
A
B
|
1
1
|
011110
011110
011111
011111
0
1
0
1
30
30
31
31
A
B
A
B
8192 Kbps/sec SBI Mode
OFFSET[9:5]
OFFSET[4:3]
TSYNC Time
Group
Slot
00000
00000
00000
00000
00001
00001
00001
00001
|
00
01
10
11
00
01
10
11
|
0
A
B
C
D
A
B
C
D
|
0
0
0
1
1
1
1
|
11110
00
30
A
100054E
Conexant
3-101