3.0 Registers
CX28394/28395/28398
3.16 System Bus Registers
Quad/x16/Octal—T1/E1/J1 Framers
8192 Kbps/sec SBI Mode
OFFSET[9:5]
OFFSET[4:3]
TSYNC Time
Group
Slot
30
30
30
31
31
31
31
11110
11110
11110
11111
11111
11111
11111
01
10
11
00
01
10
11
B
C
D
A
B
C
D
NOTE(S): Offsets which are outside the TSB timebase range result in no pulses on
TFSYNC and TMSYNC outputs.
0D7—Receive Signaling Configuration (RSIG_CR)
7
6
5
4
3
2
1
0
—
SET_RSIG
SET_SIG
UNICODE
DEBOUNCE
FRZ_OFF
FRZ_ON
THRU
SET_RSIG
SET_SIG
Force 2 ms RSIG Interrupt—Allows the processor to receive an interrupt on RSIG [addr 008]
at every CAS multiframe boundary. Applicable only to E1 mode with CAS enabled. Overrides
STACK interrupt.
0 = RSIG interrupt on signaling STACK change
1 = RSIG interrupts every 2 ms at CAS multiframe
Overwrite Robbed-Bit Signaling—Applicable only during T1 mode and function dependent
on RIDLE. When RIDLE is inactive, SET_SIG forces received robbed-bit signaling to one
before updating RSLIP time slot value. Therefore, bit 8 of each time slot received during
signaling frames 6, 12, 18, and 24 is replaced with a one. This function is particularly useful in
cross-connect and exchange systems that strip robbed-bit signaling or use different signaling
frame alignment on inbound and outbound ports.
0 = no change to receive signaling
1 = replace robbed-bit signaling
UNICODE
Inband Signaling Freeze (applicable to T1 modes only)—If UNICODE is enabled, received
ABCD signaling on all channels is searched on a per-channel basis for the 4-bit UNICODE
pattern. UNICODE pattern detection inhibits STACK. RSIG buffer updates for that channel as
long as UNICODE is present, but does not affect SIGFRZ output and is not reported to the
processor. This function is described in Bellcore TR-TSY-000303, Section 4.4.9, Revision 2,
July 1989.
0 = no effect
1 = enable UNICODE detection and per-channel signaling freeze
3-102
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
