CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.1 Address Map
Table 3-4. Address Map (5 of 5)
Default
Register
Setting (Hex)
Address
(Hex)
Block
Acronym
R/W
Description
100–11F
TPCn:
n = 0 to 31
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Transmit Per-Channel Control
Transmit Signaling Buffer
Transmit PCM Slip Buffer
Transmit PCM Slip Buffer
Receive Per-Channel Control
Receive Signaling Buffer
Receive PCM Slip Buffer
Receive PCM Slip Buffer
—
—
—
—
—
—
—
—
120–13F
140–15F
160–17F
180–19F
1A0–1BF
1C0–1DF
1E0–1FF
TSIGn:
n = 0 to 31
TSLIP_LOn:
n = 0 to 31
TSLIP_HIn:
n = 0 to 31
RPCn:
n = 0 to 31
RSIGn:
n = 0 to 31
RSLIP_LOn:
n = 0 to 31
RSLIP_HIn:
n = 0 to 31
100054E
Conexant
3-7