3.0 Registers
CX28394/28395/28398
3.2 Global Control and Status Registers
Quad/x16/Octal—T1/E1/J1 Framers
082—Master Interrupt Enable (MIE)
CX28394
7
6
5
4
3
2
1
0
—
—
—
—
MIE[3]
MIE[2]
MIE[1]
MIE[0]
CX28398 and CX28395
7
6
5
4
3
2
1
0
MIE[7]
MIE[6]
MIE[5]
MIE[4]
MIE[3]
MIE[2]
MIE[1]
MIE[0]
MIE[7:0]
MIE is a global interrupt enable for each framer. Writing a one to an MIE bit enables the
corresponding framer’s IRR bit to be latched in MIR (addr 081) and to activate the INTR*
output.
MIE0:
MIE1:
MIE2:
MIE3:
MIE4:
MIE5:
MIE6:
MIE7:
0 = Disable framer 0 IRR interrupt
1 = Enable framer 0 IRR interrupt
0 = Disable framer 1 IRR interrupt
1 = Enable framer 1 IRR interrupt
0 = Disable framer 2 IRR interrupt
1 = Enable framer 2 IRR interrupt
0 = Disable framer 3 IRR interrupt
1 = Enable framer 3 IRR interrupt
0 = Disable framer 4 IRR interrupt
1 = Enable framer 4 IRR interrupt
0 = Disable framer 5 IRR interrupt
1 = Enable framer 5 IRR interrupt
0 = Disable framer 6 IRR interrupt
1 = Enable framer 6 IRR interrupt
0 = Disable framer 7 IRR interrupt
1 = Enable framer 7 IRR interrupt
083—Test Configuration (TEST)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
—
—
—
TEST
—
TEST
Global Test Enable—Reserved for Conexant production test.
3-10
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
