CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.3 Primary Control and Status Register
3.3 Primary Control and Status Register
001—Primary Control Register (CR0)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
RESET
—
RINCF
RFRAME[3]
RFRAME[2]
RFRAME[1]
RFRAME[0]
T1/E1N
RESET
Framer Reset—When written to 1 by the microprocessor, RESET initiates an internal reset
process which initializes certain control registers to their default settings (see Table 3-4). The
internal reset process takes a maximum of 15 µsec.
The processor must not write to the control registers until the reset process is complete.
RESET remains active (1) during the reset process to allow the microprocessor to detect reset
completion. RESET also indicates a reset operation triggered by power-up, GRESET [FCR;
addr 080], or by an active low RST* pin. After RESET initialization, the following is true:
• System bus outputs (RSIGO, RPCMO, and SIGFRZ) are three-stated.
• Programmable I/O pins are configured as inputs.
• Framer control registers are set to their default values.
RINCF
Receiver Framer CRC6 include F-bit—Determines if the F-bit is included in the CRC6
remainder calculation in T1 mode (T1/E1N = 1). This bit is ignored in E1 mode (T1/E1N = 0).
0 = T1 ESF CRC6 calculation is performed on the
receive data including a 1 in place of the F-bit.
1 = TI ESF CRC6 transmit calculation is performed on
receive data including the F-bit.
100054E
Conexant
3-11
CONEXANT [ CONEXANT SYSTEMS, INC ]
