CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.1 Address Map
Table 3-4. Address Map (3 of 5)
Default
Register
Setting (Hex)
Address
(Hex)
Block
Acronym
R/W
Description
070
071
072
073
074
075
076
077
078
07B
07C
07D
07E
07F
0A0
0A1
0A2
0A3
0A4
0A5
0A6
0A7
0A8
0A9
0AA
0AB
0AC
0AD
0AE
TCR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Transmit Framer Configuration
Transmitter Configuration
Transmit Frame Format
—
—
—
00
—
—
—
—
—
—
—
—
—
—
00
00
—
—
00
00
00
00
—
—
00
00
—
—
—
TCR1
TFRM
TERROR
TMAN
Transmit Error Insert
Transmit Manual Sa-Byte/FEBE Configuration
Transmit Alarm Signal Configuration
Transmit Test Pattern Configuration
Transmit Inband Loopback Code Configuration
Transmit In-Band Loopback Code Pattern
Transmit Sa4 Byte Buffer
Transmit Sa5 Byte Buffer
Transmit Sa6 Byte Buffer
Transmit Sa7 Byte Buffer
Transmit Sa8 Byte Buffer
Bit Oriented Protocol Transceiver
Transmit BOP Code Word
Receive BOP Code Word
BOP Status
TALM
TPATT
TLB
LBP
TSA4
TSA5
TSA6
TSA7
TSA8
BOP
TBOP
RBOP
BOP_STAT
DL1_TS
DL1_BIT
DL1_CTL
RDL1_FFC
RDL1
R
R/W
R/W
R/W
R/W
R
DL1 Time Slot Enable
DL1 Bit Enable
DL1 Control
RDL #1 FIFO Fill Control
Receive Data Link FIFO #1
RDL #1 Status
RDL1_STAT
PRM
R
R/W
R/W
W
Performance Report Message
TDL #1 FIFO Empty Control
TDL #1 End Of Message Control
Transmit Data Link FIFO #1
TDL #1 Status
TDL1_FEC
TDL1_EOM
TDL1
R/W
R
TDL1_STAT
100054E
Conexant
3-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
