3.0 Registers
CX28394/28395/28398
3.1 Address Map
Quad/x16/Octal—T1/E1/J1 Framers
Table 3-4. Address Map (4 of 5)
Default
Register
Setting (Hex)
Address
(Hex)
Block
Acronym
R/W
Description
0AF
0B0
DL2_TS
R/W
R/W
R/W
R/W
R
DL2 Time-Slot Enable
00
00
00
00
—
—
00
—
—
—
00
00
00
DL2_BIT
DL2_CTL
RDL2_FFC
RDL2
DL2 Bit Enable
0B1
DL2 Control
0B2
RDL #2 FIFO Fill Control
Receive Data Link FIFO #2
RDL #2 Status
0B3
0B4
RDL2_STAT
TDL2_FEC
TDL2_EOM
TDL2
R
0B6
R/W
W
TDL #2 FIFO Empty Control
TDL #2 End Of Message Control
Transmit Data Link FIFO #2
TDL #2 Status
0B7
0B8
R/W
R
0B9
TDL2_STAT
DL_TEST1
DL_TEST2
DL_TEST3
DL_TEST4
DL_TEST5
SBI_CR
0BA
0BB
0BC
0BD
0BE
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9
0DA
0DB
0DC
0DD
0E0–0FF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
DLINK Test Configuration
DLINK Test Status
DLINK Test Status
DLINK Test Control #1 or Configuration #2
DLINK Test Control #2 or Configuration #2
System Bus Interface Configuration
Receive System Bus Configuration
Receive System Bus Sync Bit Offset
Receive System Bus Sync Time Slot Offset
Transmit System Bus Configuration
Transmit System Bus Sync Bit Offset
Transmit System Bus Sync Time Slot Offset
Receive Signaling Configuration
Signaling Reinsertion Frame Offset
Slip Buffer Status
00
00
00
00
—
—
00
—
—
—
—
—
—
—
—
—
—
RSB_CR
RSYNC_BIT
RSYNC_TS
TSB_CR
TSYNC_BIT
TSYNC_TS
RSIG_CR
RSYNC_FRM
SSTAT
STACK
R
Receive Signaling Stack
RPHASE
TPHASE
R
RSLIP Phase Status
R
TSLIP Phase Status
PERR
R
RAM Parity Status
SBCn:
R/W
System Bus Per-Channel Control
n = 0 to 31
3-6
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
